Although the guys at Technologic Systems provided a fully functional platform, if we ignore the long standing issue of "user programmable FPGA", I could not keep myself away from comments regarding the actual hardware design of the TS-7800 board. As I'm also a hardware and software (with emphasis on software) developer, I would consider the comments on this page as constructive ones with the sincere hope that they would get implemented in a future board model.
All of the issues commented here have come up while working on specialized implementations in the FPGA and it took quite a lot of time to understand some of them.
FPGA Pins for PCI
Lattice's designers had the silly idea to have special PCI bus support on 32+17 pins of their FPGA. Obviously, the 32-pins in bank 4 are for the address/data lines and the 17-pins in bank 5 are for the control lines. All these pins are on the bottom edge of the FPGA package.
The TS-7800 hardware designer had the interesting idea of using almost any other pin but the specialized ones for connecting to the PCI bus of the Marvell chip. A quick look over the provided schematic shows he has used mostly pins from the left edge of the FPGA package. And, indeed, he included 7 of the 49 specialized FPGA pins.
I know that now I'm mean, but he could have just rotated the FPGA 90 degrees clockwise and just re-route some of the tracks and the perfect pins would have been used!
Nevertheless, the board is usable and I must let you know that even 60MHz PCI clock is survivable, though not that simple to implement in FPGA to overcome wrong pins mapping.
Default FPGA Structure
The default FPGA structure, as loaded by Technologic Systems, seems to be a PCI-Wishbone bridge, with all the devices on the Wishbone bus. It has several drawbacks from my point of view:
- It is very difficult to add really high speed devices to that structure.
- It limits the PCI speed to just 50MHz instead of the maximum possible of 66MHz as the SoC supports.