Getting Ready for FPGA Development
Before starting any serious FPGA development, you must get ready for using the Technologic Systems TS-7800 without the default FPGA content. So that implies no longer relying on the SD card or NAND support in any way because while loading a new FPGA structure the access is lost and any bug in the loaded structure would prevent accessing the devices. There are several alternatives to using the SD card or the NAND, all of them implying booting from them, but having rootfs on something else. The solutions I give here are, by no means, the only ones that could be used, but I have tested all of them!
There are alternatives that make use of the available initrd, but there are also solutions for just changing the kernel command line. All of these solutions have been tested only with latest 2.6 kernels as I haven't spent any time on tweaking the Technologic System provided ones.
Before you upload your bitstream you must remember to inform the kernel that you are about to do this.
# echo offline > /sys/power/ts78xx_fpga
By doing this it will unload any driver hooks that access devices through the FPGA (such as the NAND and RTC for example). Now once you have done this step you can do your FPGA bitstream uploading. When loaded, tell the kernel you are done with your new bitstream by typing:
# echo online > /sys/power/ts78xx_fpga TS-78xx FPGA: magic=0x00b480, rev=0x03 rtc-m48t86 rtc-m48t86: rtc core: registered m48t86 as rtc0 rtc-m48t86 rtc-m48t86: battery ok NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron NAND 512MiB 3,3V 8-bit) Creating 4 MTD partitions on "gen_nand": 0x000000000000-0x000000020000 : "mbr" 0x000000020000-0x000000420000 : "kernel" 0x000000420000-0x000000820000 : "initrd" 0x000000820000-0x000020000000 : "rootfs" timeriomem_rng timeriomem_rng: 32bits from 0xc88b6044 @ 1000000us
Now the everything is well and good in the kernel.
Rootfs on USB Flash without Initrd
Actually this is pretty simple as kernel command line, but hides a rather tricky parameter because it takes a while for the kernel to detect the USB flash.
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/sde1 rw rootdelay=15"
Of course, '/dev/sde1/' is where I had rootfs.
Rootfs on NFS, still without Initrd
This is a lot trickier because there are many options that must be enabled in the kernel. I mention them just briefly in here, with the corresponding sections in the kernel configuration tree.
Enable the block layer Support for large block devices and files Networking support Networking options TCP/IP networking IP: kernel level autoconfiguration Device Drivers Block devices Network block device support File systems Network File Systems NFS client support NFS client support for NFS version 3 Root file system on NFS
A very long kernel command line is required as well. The actual meaning of each parameter can be easily found out by checking the kernel documentation.
console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.2:/RootFS_RecPlay ip=192.168.1.50::192.168.1.254:255.255.255.0:recplay:eth0:off
On the server side, after installing the nfs-kernel-server
package, the following line must be added to/etc/exports:
By copying an existing rootfs to the 'RootFS_RecPlay' directory on the server, starting the NFS server and rebooting the TS-7800 board, you should have a working NFS rootfs.
This ended as my favorite solution because when working with the FPGA, especially during development phases, I had to switch the power off and on to get out of trouble for so many times that I had lost several times the USB flash rootfs. With NFS no data is lost and no file is damaged and, in the end, that implies many hours of time not spent on recovering rootfs.
Using UrJTAG 0.9
UrJTAG 0.10 supports using the orionx GPIO pins that are hooked up to the JTAG of the FPGA. This will provide a new 'cable' in UrJTAG and will also add all the missing information on the chips found on TS-7800. There is no need for extra hardware in order to be able to use the modified UrJTAG as the whole JTAG chain is connected to 4 GPIO pins of the SoC.
The sequence of commands in UrJTAG is:
> cable ts7800 > detect > part 2 > frequency 1000000 > svf test.svf
When the commands end, you will have the specified '.svf' file loaded into the FPGA. How to obtain the '.svf' file, you should find in the documentation of the development tools you are using.
Don't be scared of using wrongly configured '.svf' files. Fortunately they include also chip ID testing scripts and only when 100% sure the programming information is for the targeted device it won't fail.