Laws of Physics in TS-7800 FPGA
Don't get fooled by the title! This page is dedicated to rules that must be obeyed when developing FPGA structures to be loaded into the Technologic Systems TS-7800 board. 99.99% of them, if broken, will most probably cause an unusable board.
Idle FPGA when reprogramming
Insure that none of the FPGA implemented devices are used in any way during the reprogramming. I know for sure that something as critical as NAND or SD card using, even if implemented in the new FPGA structure 100% identically, will gladly cope with the sudden loss of communication.
PCI Pins Mapping
Once you have defined the initial FPGA structure as Schematic/Verilog/VHDL, don't forget to check if the pins are properly mapped so you don't get two outputs or not driven inputs. Usually this step is necessary every time a pin is added to the structure. Later, the file containing the pins mapping ('.lpf' - design preferences file) can be carried from one project to another.
The PCI bus needs a working clock source in order to function. By default the FPGA uses the 25MHz input, doubles it internally, and passes it to the SoC.
As the FPGA works in a predictable way only when using a single clock or a set of correlated clocks, if you have another external clock source, try to derive the PCI clock from that one. It will save you a lot of time in debugging impossible to fix situations. The following two situations I have used and worked very well:
- 66MHz external reference, multiplied by 3 and divided by 4 gave 49.5MHz PCI clock
- 80MHz external reference, multiplied by 3 and divided by 4 gave 60MHz PCI clock
Don't get tricked by possibly matching frequencies. If you have a 75MHz external reference and you think of using the TS 25MHz clock instead of doubling and then dividing by 3 your external reference, better think again. Your oscillator is exactly 75MHz as much as the cheap crystal on the TS-7800 is exactly 25MHz. Differences sometimes as large as several kHz are not unusual!